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integrated device technology, inc. commercial temperature ranges december 1996 1996 integrated device technology, inc. dsc-2704/5 syncbififo is a trademark and the idt logo is a registered trademark of integrated device technology, inc. idt72605 idt72615 cmos syncbififo ? 256 x 18 x 2 and 512 x 18 x 2 features: two independent fifo memories for fully bidirectional data transfers 256 x 18 x 2 organization (idt 72605) 512 x 18 x 2 organization (idt 72615) synchronous interface for fast (20ns) read and write cycle times each data port has an independent clock and read/write control output enable is provided on each port as a three-state control of the data bus built-in bypass path for direct data transfer between two ports two fixed flags, empty and full, for both the a-to-b and the b-to-a fifo programmable flag offset can be set to any depth in the fifo the synchronous bififo is packaged in a 64-pin tqfp (thin quad flatpack), 68-pin pga and 68-pin plcc industrial temperature range (-40oc to +85oc) is avail- able, tested to military electrical specifications description: the idt72605 and idt72615 are very high-speed, low- power bidirectional first-in, first-out (fifo) memories, with synchronous interface for fast read and write cycle times. the syncbififo ? is a data buffer that can store or retrieve information from two sources simultaneously. two dual-port fifo memory arrays are contained in the syncbififo; one data buffer for each direction. the syncbififo has registers on all inputs and outputs. data is only transferred into the i/o registers on clock edges, hence the interfaces are synchronous. each port has its own independent clock. data transfers to the i/o registers are gated by the enable signals. the transfer direction for each port is controlled independently by a read/write signal. individ- ual output enable signals control whether the syncbififo is driving the data lines of a port or whether those data lines are in a high-impedance state. bypass control allows data to be directly transferred from input to output register in either direction. the syncbififo has eight flags. the flag pins are full, empty, almost-full, and almost-empty for both fifo memo- ries. the offset depths of the almost-full and almost-empty flags can be programmed to any location. the syncbififo is fabricated using idt? high-speed, submicron cmos technology. clk a flag logic memory array 512 x 18 256 x 18 input register mux output register high z control output register input register clk b mux memory array 512 x 18 256 x 18 high z control flag logic reset logic power supply r/ w a cs a a 2 a 1 a 0 ef ab pae ab paf ab ff ab oe b r/ w b en b en a oe a rs ef ba pae ba paf ba ff ba v cc gnd 3 byp b m p interface 7 d b0 -d b17 d a0 -d a17 2704 drw 01 functional block diagram for latest information contact idt's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.18 1
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 2 pin configurations plcc top view gnd gnd d b16 d b15 d b17 paf ab ef ab gnd a 2 v cc d a17 gnd d a16 clk a en a a 0 a 1 abcdef g hjkl 01 02 03 04 05 06 07 08 09 10 11 ff ab r/ w a pin 1 designator 2704 drw 02 gnd d a15 gnd pae ab cs a rs gnd oe a d b4 d b5 d b6 d b7 d b8 d b11 d b10 d b9 d b12 d b13 d b14 d b3 d b2 d b1 d b0 clk b en b byp b ff ba paf ba d a0 d a1 d a2 d a3 d a4 d a5 d a6 d a7 d a8 d a9 d a10 d a11 d a12 d a13 d a14 v cc r/ w b oe b pae ba ef ba v cc g68-1 pga top view 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 10 11 18 19 20 21 22 23 24 25 26 17 16 15 14 13 12 52 51 50 49 48 47 46 45 44 53 54 55 56 57 60 59 58 35 43 42 41 40 39 38 37 36 34 33 32 31 30 29 28 27 clk b d b0 d b2 d b1 byp b oe b en b r/w rs paf ba pae ba ff ba ef ba gnd d a2 d a1 d a0 b gnd d a3 d a4 gnd d a15 d a13 d a14 d a12 d a11 d a10 v cc gnd d a5 d a6 d a7 d a8 d a9 d b9 v cc d b15 gnd d b8 d b7 d b6 d b14 d b13 d b12 d b11 d b10 gnd gnd d b5 d b4 d b3 ef ab d b16 d b17 a 2 v cc a 1 d a16 d clk a a17 a 0 cs a en a r/w a ff ab pae ab paf ab oe a 2704 drw 03 j68-1
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 3 pin configurations pin 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 da 1 da 0 ef ba ff ba pae ba paf ba gnd byb b oe b en b r/ w b clk b rs db 0 db 1 db 2 db 3 db 4 gnd db 5 db 6 db 7 db 8 db 9 db 10 db 11 db 12 db 13 db 14 gnd db 15 db 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 da 16 da 17 clk a r/ w a en a cs a a 0 a 1 a 2 v cc ef ab ff ab pae ab paf ab oe a db 17 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2704 drw 04 da 2 da 3 da 4 da 5 da 6 da 7 da 8 da 9 gnd da 10 da 11 da 12 da 13 da 14 da 15 vcc pn64-1 tqfp top view
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 4 pin description symbol name i/o description d a0 -d a17 data a i/o data inputs & outputs for the 18-bit port a bus. cs a chip select a i port a is accessed when cs a is low. port a is inactive if cs a is high. r/ w a read/write a i this pin controls the read or write direction of port a. if r/ w a is low, data a input data is written into port a. if r/ w a is high, data a output data is read from port a. in bypass mode, when r/ w a is low, message is written into a ? b output register. if r/ w a is high, message is read from b ? a output register. clk a clock a i clk a is typically a free running clock. data is read or written into port a on the rising edge of clk a . en a enable a i when en a is low, data can be read or written to port a. when en a is high, no data transfers occur. oe a output enable a i when r/ w a is high , port a is an output bus and oe a controls the high-impedance state of d a0 -d a17 . if oe a is high, port a is in a high-impedance state. if oe a is low while cs a is low and r/ w a is high, port a is in an active (low-impedance) state. a 0 , a 1 , a 2 addresses i when cs a is asserted, a 0 , a 1 , a 2 and r/ w a are used to select one of six internal resources. d b0 -d b17 data b i/o data inputs & outputs for the 18-bit port b bus. r/ w b read/write b i this pin controls the read or write direction of port b. if r/ w b is low, data b input data is written into port b. if r/ w b is high, data b output data is read from port b. in bypass mode, when r/ w b is low, message is written into b ? a output register. if r/ w b is high, message is read from a ? b output register. clk b clock b i clock b is typically a free running clock. data is read or written into port b on the rising edge of clk b . en b enable b i when en b is low, data can be read or written to port b. when en b is high, no data transfers occur. oe b output enable b i when r/ w b is high , port b is an output bus and oe b controls the high-impedance state of d b0 -d b17 . if oe b is high, port b is in a high-impedance state. if oe b is low while r/ w b is high, port b is in an active (low-impedance) state. ef ab a ? b empty flag o when ef ab is low, the a ? b fifo is empty and further data reads from port b are inhibited. when ef ab is high, the fifo is not empty. ef ab is synchronized to clk b . in the bypass mode, ef ab high indicates that data d a0 -d a17 is available for passing through. after the data d b0 -d b17 has been read, ef ab goes low. pae ab a ? b o when pae ab is low, the a ? b fifo is almost empty. an almost empty fifo contains less programmable than or equal to the offset programmed into pae ab register. when pae ab is high, the almost-empty flag a ? b fifo contains more than offset in pae ab register. the default offset value for pae ab register is 8. pae ab is synchronized to clk b . paf ab a ? b o when paf ab is low, the a ? b fifo is almost full. an almost full fifo contains greater than programmable the fifo depth minus the offset programmed into paf ab register. when paf ab is high, almost-full flag the a ? b fifo contains less than or equal to the depth minus the offset in paf ab register. the default offset value for paf ab register is 8. paf ab is synchronized to clk a . ff ab a ? b full flag o when ff ab is low, the a ? b fifo is full and further data writes into port a are inhibited. when ff ab is high, the fifo is not full. ff ab is synchronized to clk a . in bypass mode, ff ab tells port a that a message is waiting in port bs output register. if ff ab is low, a bypass message is in the register. if ff ab is high, port b has read the message and another message can be written into port a. ef ba b ? a empty flag o when ef ba is low, the b ? a fifo is empty and further data reads from port a are inhibited. when ef ba is high, the fifo is not empty. ef ba is synchronized to clk a . in the bypass mode, ef ba high indicates that data d b0 -d b17 is available for passing through. after the data d a0 -d a17 has been read, ef ba goes low on the following cycle. pae ba b ? a o when pae ba is low, the b ? a fifo is almost empty. an almost empty fifo contains less programmable than or equal to the offset programmed into pae ba register. when pae ba is high, the almost-empty flag b ? a fifo contains more than offset in pae ba register. the default offset value for pae ba register is 8. pae ba is synchronized to clk a . paf ba b ? a o when paf ba is low, the b ? a fifo is almost full. an almost full fifo contains greater than programmable the fifo depth minus the offset programmed into paf ba register. when paf ba is high, almost-full flag the b ? a fifo contains less than or equal to the depth minus the offset in paf ba register. the default offset value for paf ba register is 8. paf ba is synchronized to clk b . 2704 tbl 01
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 5 recommended dc operating conditions symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd supply voltage 0 0 0 v v ih input high voltage 2.0 v v il (1) input low voltage 0.8 v note: 2704 tbl 04 1. 1.5v undershoots are allowed for 10ns once per cycle. pin description (continued) symbol name i/o description 2704 tbl 02 ff ba b ? a full flag o when ff ba is low, the b ? a fifo is full and further data writes into port b are inhibited. when ff ba is high, the fifo is not full. ff ba is synchronized to clk b . in bypass mode, ff ba tells port b that a message is waiting in port as output register. if ff ba is low, a bypass message is in the register. if ff ba is high, port a has read the message and another message can be written into port b. byp b port b bypass o this flag informs port b that the synchronous bififo is in bypass mode. when byp b is flag low, port a has placed the fifo into bypass mode. if byp b is high, the synchronous bififo passes data into memory. byp b is synchronized to clk b . rs reset i a low on this pin will perform a reset of all synchronous bififo functions. v cc power there are three +5v power pins for the plcc and pga packages and two for the tqfp. gnd ground there are seven ground pins for the plcc and pga packages and four for the tqfp. absolute maximum ratings (1) symbol rating com?. mil. unit v term terminal voltage C0.5 to +7.0 C0.5 to +7.0 v with respect to ground t a operating 0 to +70 C55 to +125 c temperature t bias temperature C55 to +125 C65 to +135 c under bias t stg storage C55 to +125 C65 to +150 c temperature i out dc output current 50 50 ma note: 2704 tbl 03 1. stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2704 tbl 05 capacitance (t a = +25 c, f = 1.0mhz) symbol parameter conditions max. unit c in (2) input capacitance v in = 0v 10 pf c out (1,2) output capacitance v out = 0v 10 pf notes: 1. with output deselected. 2. characterized values, not currently tested. 2704 tbl 06 dc electrical characteristics (commercial: v cc = 5v 10%, t a = 0 c to +70 c) idt72615l idt72605l commercial t clk = 20, 25, 35, 50ns symbol parameter min. typ. max. unit i il (1) input leakage current (any input) C1 1 m a i ol (2) output leakage current C10 10 m a v oh output logic "1" voltage i out = C2ma 2.4 v v ol output logic "0" voltage i out = 8ma 0.4 v i cc (3) average v cc power supply current 230 ma notes: 1. measurements with 0.4v v in v cc . 2. oea , oeb 3 v ih ; 0.4 v out v cc . 3. tested with outputs open. testing frequency f=20mhz
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 6 ac test conditions in pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 2 2704 tbl 07 +5v 1.1k w 680 w 30pf* d.u.t. 2704 drw 05 ac electrical characteristics (commercial: v cc = 5v 10%, t a = 0 c to +70 c) commercial 72615l20 72615l25 72615l35 72615l50 72605l20 72605l25 72605l35 72605l50 symbol parameter min. max. min. max. min. max. min. max. unit timing figures f clk clock frequency 50 40 28 20 mhz t clk clock cycle time 20 25 35 50 ns 4,5,6,7 t clkh clock high time 8 10 14 20 ns 4,5,6,7,12,13,14,15 t clkl clock low time 8 10 14 20 ns 4,5,6,7,12,13,14,15 t rs reset pulse width 20 25 35 50 ns 3 t rss reset set-up time 12 15 21 30 ns 3 t rsr reset recovery time 12 15 21 30 ns 3 t rsf reset to flags in intial state 27 28 35 50 ns 3 t a data access time 3 10 3 15 3 21 3 25 ns 5,7,8,9,10,11 t cs control signal set-up time (1) 6 6 8 10 ns 4,5,6,7,8,9,10,11, 12, 13,14,15 t ch control signal hold time (1) 1 1 1 1 ns 4,5,6,7,10,11,12, 13, 14,15 t ds data set-up time 6 6 8 10 ns 4,6,8,9,10,11 t dh data hold time 1 1 1 1 ns 4,6 t oe output enable low to 3 10 3 13 3 20 3 28 ns 5,7,8,9,10,11 output data valid (2) t olz output enable low to data 0 0 0 0 ns 5,7,8,9,10,11 bus at low-z (2) t ohz output enable high to data 3 10 3 13 3 20 3 28 ns 5,7,10,11 bus at high-z (2) t ff clock to full flag time 10 15 21 30 ns 4,6,10,11 t ef clock to empty flag time 10 15 21 30 ns 5,7,8,9,10,11 t pae clock to programmable 12 15 21 30 ns 12,14 almost empty flag time t paf clock to programmable 12 15 21 30 ns 13,15 almost full flag time t skew1 skew between clk a & clk b 10 12 17 20 ns 4,5,6,7,8,9,10,11 for empty/full flags (2) t skew2 skew between clk a & clk b 17 19 25 34 ns 4, 7,12,13,14,15 for programmable flags (2) notes: 1. control signals refer to cs a , r/ w a , en a , a 2 , a 1 , a 0 , r/ w b , en b . 2. minimum values are guaranteed by design. 2704 tbl 08 or equivalent circuit figure 2. output load * includes jig and scope capacitances.
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 7 notes: 1. upper syncbififo only is used in 18- to 18-bit configuration. 2. control a consists of r/ w a , en a , oe a , cs a , a 2 , a 1 , a 0 . control b consists of r/ w b , en b , oe b . figure 1. 36- to 36-bit processor interface configuration. reset reset is accomplished whenever the reset ( rs ) input is taken to a low state with cs a , en a and en b high. during reset, both internal read and write pointers are set to the first location. a reset is required after power up before a write operation can take place. the a ? b and b ? a fifo empty flags ( ef ab , ef ba ) and programmable almost empty flags ( pa eab , pa eba ) will be set to low after t rsf . the a ? b and b ? a fifo full flags ( ff ab , ff ba ) and programmable almost full flags ( paf ab , paf ba ) will be set to high after t rsf . after the reset, the offsets of the almost-empty flags and almost- full flags for the a ? b and b ? a fifo offset default to 8. port a interface the syncbififo is straightforward to use in micro-pro- cessor-based systems because each port has a standard microprocessor control set. port a interfaces with micropro- cessor through the three address pins (a 2 -a 0 ) and a chip select cs a pins. when cs a is asserted, a 2 ,a 1 ,a 0 and r/ w a are used to select one of six internal resources (table 1). with a 2 =0 and a 1 =0, a 0 determines whether data can be read out of output register or be written into the fifo (a 0 =0), or the data can pass through the fifo through the bypass path (a 0 =1). with a 2 =1, four programmable flags (two a ? b fifo pro- grammable flags and two b ? a fifo programmable flags) can be selected: the a ? b fifo almost-empty flag offset (a 1 =0, a 0 =0), a ? b fifo almost-full flag offset (a 1 =0, a 0 =1), b ? a fifo almost-empty flag offset (a 1 =1, a 0 =0), b ? a fifo almost-full flag offset (a 1 =1, a 0 =1). port a is disabled when csa is deasserted and data a is in high-impedance state. clk data addr, i/0 control logic ram a idt syncbififo data b clk control b b system clock a control logic clk microprocessor a microprocessor b data addr, i/0 ram b system clock b idt syncbififo data b clk control b b data a clk control a a data a clk control a a 2704 drw 06 functional description idts syncbififo is versatile for both multiprocessor and peripheral applications. data can be stored or retrieved from two sources simultaneously. the syncbififo has registers on all inputs and outputs. data is only transferred into the i/o registers on clock edges, hence the interfaces are synchronous. two dual-port fifo memory arrays are contained in the syncbififo; one data buffer for each direction. each port has its own independent clock. data transfers to the i/o registers are gated by the enable signals. the transfer direction for each port is con- trolled independently by a read/write signal. individual output enable signals control whether the syncbififo is driving the data lines of a port or whether those data lines are in a high- impedance state. the processor connected to port a of the bififo can send or receive messages directly to the port b device using the 18-bit bypass path. the syncbififo can be used in multiples of 18-bits. in a 36- to 36-bit configuration, two syncbififos operate in parallel. both devices are programmed simultaneously, 18 data bits to each device. this configuration can be extended to wider bus widths (54- to 54-bits, 72- to 72-bits, etc.) by adding more syncbififos to the configuration. figure 1 shows multiple syncbififos configured for multiprocessor communication. the microprocessor or microcontroller connected to port a controls all operations of the syncbififo. thus, all port a interface pins are inputs driven by the controlling processor. port b interfaces with a second processor. the port b control pins are inputs driven by the second processor.
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 8 data a cs cs a r/ w w a en en a oe oe a i/o port a operation 0 0 0 0 i data a is written on clka 1 . this write cycle immediately following low-impedance cycle is prohibited. note that even though oe a = 0, a low logic level on r/w a , once qualified by a rising edge on clk a, will put data a into a high-impedance state. 0 0 0 1 i data a is written on clka 1 0 0 1 x i data a is ignored 0 1 0 0 o data is read (1) from ram array to output register on clka 1 , data a is low-impedance 0 1 0 1 o data is read (1) from ram array to output register on clka 1 , data a is high-impedance 0 1 1 0 o output register does not change (2) , data a is low-impedance 0 1 1 1 o output register does not change (2) , data a is high-impedance 1 0 x x i data a is ignored (3) 1 1 x x o data a is high-impedance (3) notes: 1. when a 2 a 1 a 0 = 000, the next b ? a fifo value is read out of the output register and the read pointer advances. if a 2 a 1 a 0 = 001, the bypass path is selected and bypass data from the port b input register is read from the port a output register. if a 2 a 1 a 0 0 = 1xx, a flag offset register is selected and its offset is read out through port a output register. 2. regardless of the condition of a 2 a 1 a 0 , the data in the port a output register does not change and the b ? a read pointer does not advance. 3. if cs a# is high, then byp b is high. no bypass occur under this condition. 2704 tbl 09 bypass path the bypass paths provide direct communication between port a and port b. there are two full 18-bit bypass paths, one in each direction. during a bypass operation, data is passed directly between the input and output registers, and the fifo memory is undisturbed. port a initiates and terminates all bypass operations. the bypass flag, byp b , is asserted to inform port b that a bypass operation is beginning. the bypass flag state is controlled by the port a controls, although the byp b signal is synchronized to clk b . so, byp b is asserted on the next rising edge of clk b when a 2 a 1 a 0 =001and cs a is low. when port a returns to normal fifo mode (a 2 a 1 a 0 =000 or cs a is high), byp b is deasserted on the next clk b rising edge. once the syncbififo is in bypass mode, all data transfers are controlled by the standard port a (r/ w a , clk a , en a , oe a ) and port b (r/ w b , clk b , en b , oe b ) interface pins. each bypass path can be considered as a one word deep fifo. data is held in each input register until it is read. since the controls of each port operate independently, port a can be reading bypass data at the same time port b is reading bypass data. when r/ w a and en a is low, data on pins d a0 -d a17 is written into port a input register. following the rising edge of clk a for this write, the a ? b full flag ( ff ab ) goes low. subsequent writes into port a are blocked by internal logic until ff ab goes high again. on the next clkb rising edge, the a ? b empty flag ( ef ab ) goes high indicating to port b that data is available. once r/ w b is high and en b is low, data is read into the port b output register. oe b still controls whether port b is in a high-impedance state. when oe b is low, the output register data appears at d b0 -d b17 . ef ab goes low following the clk b rising edge for this read. ffab goes high on the next clk a rising edge, letting port a know that another word can be written through the bypass path. bypass data transfers from port b to port a work in a similar manner with efb a and ffb a indicating the port a output register state. when the port a address changes from bypass mode (a 2 a 1 a 0 =001) to fifo mode (a 2 a 1 a 0 =000) on the rising edge of clk a , the data held in the port b output register may be overwritten. unless port a monitors the byp b pin and waits for port b to clock out the last bypass word, data from the a ? b fifo will overwrite data in the port b output register. byp b will go high on the rising edge of clk b signifying that port b has finished its last bypass operation. port b must read any bypass data in the output register on this last clk b clock or it is lost and the syncbififo returns to fifo operations. it is especially important to monitor byp b when clk b is much slower than clk a to avoid this condition. byp b will also go high after cs a is brought high; in this manner the port b bypass data may also be lost. since the port a processor controls cs a and the bypass mode, this scenario can be handled for b ? a bypass data. the port a processor must be set up to read the last bypass word before leaving bypass mode. table 1. port a operation control signals
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 9 table 2. accessing port a resources using cs cs a , a 2 , a 1 , and a 0. number of words in fifo from to ef ef pae pae paf paf ff ff 0 0 low low high high 1 n high low high high n+1 d-(m+1) high high high high d-m d-1 high high low high d d high high low low notes: n = programmable empty offset ( pae ab register or pae ba register) m = programmable full offset ( paf ab register or paf ba register) d = fifo depth (idt72605 = 256 words, idt72615= 512 words) 2704 tbl 12 table 4. internal flag truth table. 17161514131211109876543210 pae ab register x x xxxxxxx a ? b fifo almost-empty flag offset 17161514131211109876543210 paf ab register x x xxxxxxx a ? b fifo almost-full flag offset 17161514131211109876543210 pae ba register x x xxxxxxx b ? a fifo almost-empty flag offset 17161514131211109876543210 paf ba register x x xxxxxxx b ? a fifo almost-full flag offset note: 1. bit 8 must be set to 0 for the idt72605 (256 x 18) synchronous bififo. 2704 tbl 11 table 3. flag offset register format. programmable flags the idt syncbififo has eight flags: four flags for a ? b fifo ( ef ab , pae ab , paf ab , ff ab ), and four flags for b ? a fifo ( ef ba , pae ba , paf ba , ff ba ). the empty and full flags are fixed, while the almost empty and almost full offsets can be set to any depth through the flag offset registers (see table 3). the flags are asserted at the depths shown in the flag truth table (table 4). after reset, the programmable flag offsets are set to 8. this means the almost empty flags are asserted at empty +8 words deep, and the almost full flags are asserted at full -8 words deep. the pae ab is synchronized to clk b , while pae ab is syn- chronized to clk a ; and pae ba is synchronized to clk a , while pae ba is synchronized to clk b . if the minimum time (t skew2 ) between a rising clk b and a rising clk a is met, the flag will change state on the current clock; otherwise, the flag may not change state until the next clock rising edge. for the specific flag timings, refer to figures 12-15. port b control signals the port b control signal pins dictate the various operations shown in table 5. port b is independent of cs a . r/ w b and en b lines determine when data can be written or read in port b. if r/ w b and en b are low, data is written into input register, and on low-to-high transition of clk b data is written into 2704 tbl 10 cs cs a a 2 a 1 a 0 read write 0000 b ? a fifo a ? b fifo 0001 18-bit bypass path 0100a ? b fifo almost-empty flag offset 0101 a ? b fifo almost-full flag offset 0110b ? a fifo almost-empty flag offset 0111 b ? a fifo almost-full flag offset 1 x x x port a disabled port a control signals the port a control signals pins dictate the various opera- tions shown in table 2. port a is accessed when cs a is low, and is inactive if cs a is high. r/ w a and en a lines determine when data a can be written or read. if r/ w a and en a are low, data is written into input register on the low-to-high transition of clk a . if r/ w a is high and oe a is low, data comes out of bus and is read from output register into three-state buffer. refer to pin descriptions for more information.
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 10 data b r/ w w b en en b oe oe b i/o port b operation 0 0 0 i data b is written on clkb - . this write cycle immediately following output low- impedance cycle is prohibited. note that even though oe b = 0, a low logic level on r/ w b , once qualified by a rising edge on clk b, will put data b into a high-impedance state. 0 0 1 i data b is written on clkb - . 0 1 x i data b is ignored 1 0 0 o data is read (1) from ram array to output register on clkb 1 , data b is low impedance 1 0 1 o data is read (1) from ram array to output register on clkb 1 , data b is high impedance 1 1 0 o output register does not change (2) , data b is low-impedance 1 1 1 o output register does not change (2) , data b is high-impedance notes: 2704 tbl 13 1. when a 2 a 1 a 0 = 000 or 1xx, the next a ? b fifo value is read out of the output register and the read pointer advances. if a 2 a 1 a 0 = 001, the bypass path is selected and bypass data is read from the port b output register. 2. regardless of the condition of a 2 a 1 a 0 , the data in the port b output register does not change and the a ? b read pointer does not advance. table 5. port b operation control signals. input register and the fifo memory. if r/ w b is high and oe b is low, data comes out of bus and is read from output register into three-state buffer. in bypass mode, if r/ w b is low, bypass messages are transferred into b ? a output register. if r/ w a is high, bypass messages are transferred into a ? b output register. refer to pin descriptions for more information.
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 11 rs t rsf t rs t rsf t rsr ef ab, pae ab, ef ba, pae ba ef ab, pae ab, ef ba, pae ba cs a, en a, en b t rss 2704 drw 07 figure 3. reset timing clk t clkl t cs t clk t clkh t ch no operation a en a b cs a a , 2 a , 0 a , 1 r/w a ff ab t ff t ds t dh data in valid t skew1 read no read operation clk d a0 -d a17 2704 drw 08 t ff figure 4. port a (a ? b) write timing
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 12 figure 5. port a (b ? a) read timing figure 6. port b (b ? a) write timing clk t clkl t clk t clkh t ch t ef valid data t skew1 no write write a en a clk b ba cs a a , 2 a , 0 a , 1 ef d a0 -d a17 t ef t cs t a no operation t oe t ohz t olz oe a r/w a 2704 drw 09 clk t clkl t cs t ff t clk t clkh t ch no operation t ff t ds t dh data in valid t skew1 read no read operation b en b clk a ba r/w b ff d b0 -d b17 2704 drw 10
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 13 figure 7. port b (a ? b) read timing t clkl t clk t clkh t ch t ef valid data t skew1 no write operation write clk b clk a en b ab ef d b0 -d b17 t ef t cs t a no operation t oe t ohz t olz oe b r/w b 2704 drw 11
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 14 note: 1. when t skew1 3 minimum specification, t frl(max.) = t clk + t skew1 t skew1 < minimum specification, t frl(max.) = 2t clk + t skew1 or t clk + t skew1 the latency timing applies only at the empty boundary ( ef = low). figure 8. a ? b first data word latency after reset for simultaneous read and write d 0 (first valid write) clk a t cs t ds d 1 d 2 d 3 t frl t skew1 t cs t ef d 0 d 1 t a t a t olz t oe a , 2 a , 0 a , 1 clk b cs , en a d a0 -d a17 r/w a r/w b en b d b0 -d b17 oe b ab ef 2704 drw 12 (1) a
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 15 note: 1. when t skew1 3 minimum specification, t frl(max.) = t clk + t skew1 t skew1 < minimum specification, t frl(max.) = 2t clk + t skew1 the latency timing apply only at the empty boundary ( ef = low). figure 9. b ? a first data word latency after reset for simultaneous read and write a , 2 a , 0 a , 1 d 0 (first valid write) clk b t cs t ds d 1 d 2 d 3 t cs t ef d 0 d 1 t a t a t olz t oe en b d b0 -d b17 r/w b r/w a cs , en a d a0 -d a17 oe a ba ef clk a t frl t skew1 2704 drw 13 (1) a
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 16 notes: 1. when cs a is brought high, a ? b bypass mode will switch to fifo mode on the following clk a low-to-high transition. 2. after the bypass operation is completed, the byp b goes from low-to-high; this will reset all bypass flags. the bypass path becomes available for the next bypass operation. 3. when a-side changed from bypass mode into fifo mode, b-side only has one cycle to read the bypass data. on the next cycle, b-side will be forced back to fifo mode. figure 10. a ? b bypass timing clk a t ch t skew1 data output t a t olz t oe a , 2 a , 0 a , 1 clk b en a d a0 -d a17 r/w a r/w b en b d b0 -d b17 oe b ab ef t cs a , 0 a , 2 a , 1 = 001 t cs t ff t ff data input bypass flag fifo flag t ff t ds t skew1 t skew1 t cs t ef t ef t ef bypass flag fifo flag t ohz ab ff cs a b byp fifo flag t ch 2704 drw 14
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 17 clk b clk a d b0 -d b17 r/w b r/w a en a d a0 -d a17 oe a ba ef a , 2 a , 0 a , 1 ba ff en b data output t a t olz t oe t cs data input bypass flag fifo flag t ds t skew1 t ef t ef t ef bypass flag fifo flag t ohz fifo flag t cs t ch t skew1 t ef t skew1 t cs cs a b byp t ff t ff t ff t ff t cs t cs = 001 a , 0 a , 2 a , 1 t skew1 2704 drw 15 notes: 1. when cs a is brought high, a ? b bypass mode will switch to fifo mode on the following clk a going low-to-high. 2. after the bypass operation is completed, the byp b goes from low-to-high; this will reset all bypass flags. the bypass path becomes available for the next bypass operation. 3. when a-side changed from bypass mode into fifo mode, b-side only has one cycle to read the bypass data. on the next cycle, b-side will be forced back to fifo mode. figure 11. b ? a bypass timing
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 18 notes: 1. t skew2 the minimum time between a rising clk a edge and a rising clk b edge for pae ab to change during that clock cycle. if the time between the rising edge of clk a and the rising edge of clk b is less than t skew , then pae ab may not go high until the next clkb rising edge. 2. if a read is performed on this rising edge of the read clock, there will be empty + (n + 1) words in the fifo when pae goes low. figure 12. a ? b programmable almost-empty flag timing notes: 1. t skew2 is the minimum time between a rising clk b edge and a rising clk a edge for paf ab to change during that clock cycle. if the time between the rising edge of clk b and the rising edge of clk a is less than t skew2 , then paf ab may not go high until the next clk a rising edge. 2. if a write is performed on this rising edge of the write clock, there will be full - (m + 1) words in the fifo when paf goes low. figure 13. a ? b programmable almost-full flag timing (2) clk t cs t ch a t clkl t clkh t pae t pae t skew2 (1) t cs t ch write read en a (r/w = 1) b clk b pae ab en a (r/w = 0) a n words in fifo n+1 words in fifo 2704 drw 16 clk t cs t ch a t clkl t clkh t paf t cs t ch write read en b (r/w = 1) b clk b paf ab en a (r/w = 0) a (2) t paf full - (m+1) words in fifo full - m words in fifo 2704 drw 17
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 19 notes: 1. t skew2 is the minimum time between a rising clk b edge and a rising clk a edge for pae ba to change during that clock cycle. if the time between the rising edge of clk b and the rising edge of clk a is less than t skew2 , then pae ba may not go high until the next clk a rising edge. 2. if a read is performed on this rising edge of the read clock, there will be empty + (n - 1) words in the fifo when pae goes low. figure 14. b ? a programmable almost-empty flag timing notes: 1. t skew2 is the minimum time between a rising clk b edge and a rising clk a edge for paf ba to change during that clock cycle. if the time between the rising edge of clk b and the rising edge of clk a is less than t skew2 , then paf ba may not go high until the next clk a rising edge. 2. if a write is performed on this rising edge of the write clock, there will be full - (m + 1) words in the fifo when paf goes low. figure 15. b ? a programmable almost-full flag timing clk t cs t ch b t clkl t clkh t paf t cs t ch write read en a (r/w = 1) a clk a paf ba en b (r/w = 0) a (2) t paf t skew2 (1) full - (m+1) words in fifo full - m words in fifo 2704 drw 19 clk t cs t ch b t clkl t clkh t pae t pae t skew2 (1) t cs t ch write read en a (r/w = 1) a clk a pae ba en b (r/w = 0) a n words in fifo (2) n+1 words in fifo 2704 drw 18
idt72605/idt72615 cmos syncbififo 256 x 18 x 2 and 512 x 18 x 2 commercial temperature range 5.18 20 ordering information xxxxx idt device type xxx x x power speed package process/ temperature range blank 256 x 18 parallel synchronous bidirectional fifo 512 x 18 parallel synchronous bidirectional fifo low power commercial (0 c to +70 c) clock cycle time (t clk ) in ns 72605 72615 l 20 25 35 50 g j pf 68-pin pga 68-pin plcc 64-pin tqfp 2704 drw 20

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